14b 560kS/s pipeline ADC (Analog/ Digital Converter)
- Effective Number of Bits: 13.5b (SNDR=83dB signal-to-noise-and-distortion-ratio)
- Power supply 3.3V, Power Consumption 2,4mW
- 0.35um CMOS Technology
- Low input sampling capacitor of 4pF
- Fully differential analog voltage input (3 pins: Vin+, Vin- with adjustable common mode level Vcm)
- Chip area ~ 14mm²
Reprint of the publication from 3rd IEE International Conference on Advanced A/D and D/A Conversion Techniques and their Applications (ADDA’02) Prague, Czech Republic, June 2002