14b 30kS/s serial ADC

14b 30kS/s cyclic/algorithmic serial ADC (Analog/ Digital Converter)

• Effective Number of Bits: 13.5b (SNDR=83dB signal-to-noise-and-distortion-ratio)
• Power supply 3.3V, Power Consumption 170µW
• 0.35um CMOS Technology
• Low input sampling capacitor of 4pF
• Pseudo differential analog voltage input (3 pins: Vin+, Vin- with adjustable common mode level Vcm)
• Layout chip area < 0,8mm²
• External clock rate 3-4MHz

An analog approach to compensate for OpAmp offset and finite gain in SC circuitry: A case study of a cyclic RSD ADC

Reprint of the publication from 3^rd  IEE International Conference on Advanced A/D and D/A Conversion Techniques and their Applications (ADDA’02) Prague, Czech Republic, June 2002

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