12b 1MS/s cyclic/algorithmic serial ADC (Analog/ Digital Converter)
- Effective Number of Bits: 11b (SNDR=68dB signal-to-noise-and-distortion-ratio)
- Power supply 3.3V
- 0.35um CMOS Technology
- Low input sampling capacitor of 7pF
- Fully differential analog voltage input (3 pins: Vin+, Vin- with adjustable common mode level Vcm)
- Layout chip area 0.75mm²
Reprint of the publication from 3rd IEE International Conference on Advanced A/D and D/A Conversion Techniques and their Applications (ADDA’02) Prague, Czech Republic, June 2002