Diploma/Master thesis

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Send us email to richard.izak@continiumtech.com

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1. Digital RTL implementation of the JESD204 transmitter and receiver

Today’s wireless infrastructure (BTS base stations) transceivers use DSP blocks implemented in digital SoC chips or in digital programmable FPGA devices and separate analog RF frontends, the interface between both causes data bottleneck. A radio frequency receiver (Rx) frontend of base stations consists of pre-amplifiers (LNA), mixers and one A/D converters (ADC), where the ADC has the task to digitize the whole 500MHz communication band, usually this delivers digital data in the range of some Gb/s (giga-bit per second). Recent active array 5G base stations work with the principle of active beam-forming towards the 5G wireless users, and integrate up to 8×8 or 16×16 MIMO transceivers (multipath wireless propagation via 8 Rx and Tx or up to 16 Tx and Rx).

The digital interface of such beam-forming wireless RF frontend with all the ADCs would require either up 16 x 14b = 224 pins for parallel connectivity to digital base band SoC or a high speed serial interface with just few pins. The serial interface JESD204 for multi-channel ADCs/DACs towards digital SoC/FPGA has been introduced in 2006 and updated in 2011 for speeds between 312,5MB/s and 12,5GB/s and 2017 for speed up to 32GB/s. Continium Technologies as data converter analog design house integrates ADC and DAC in CMOS, and thus requires the digital implementation of JESD204B/C transmitter (ADC-side) and receiver (DAC-side) to serve our data converters.

Recommended introductory reading:

A.Desimone: Grasp the Critical Issues for a Functioning JESD204B Interface. ADI application note MS-2448

Del Jones: JESD204B Subclasses (part 1&2). ADI application note MS-2672 and MS-2677

Del Jones: JESD204C Primer: What’s New and in It for You- Part 1& 2 /July 2019

The diploma/master thesis task includes:

* Digital RTL (register-transfer-level) code implementation of the Tx and Rx of JESD204B/C including top level simulation level in CAD tools
* Synthesis of the developed Tx and Rx code on two different programmable FPGA devices to verify the full functionality of the digital IP cores, lab evaluation and test with FPGA boards
* Synthesis towards the selected nano-meter CMOS technology including timing simulation (STA analysis) and verification

Required skills:

* Experience of HDL (Hardware description language) Verilog or VHDL,  and RTL level simulation including CAD tool experience like Synopsys, Cadence, IcarusHDL.
* Logic verification and logic simulation on RTL level or on transistor level
* first experience with HDL Synthesis for integrated circuits
* Static Timing Analysis (STA), Power estimation and optimization, circuit analysis & debugging

2. Design rule translation from iPDK to a customized layout editor

Semiconductor foundries provide electronic companies for their micro-chip development the technology-related data in the form of PDK (process development kits). These PDKs contain list of available devices i.e. transistors, their simulation SPICE models on the one hand, and physical mask layout specific data on the other. These mask layout data in PDKs are referred to as Design Rules (DR)  and describe constraints such as minimum transistor width/length, number of transistor fingers, capacitor/resistor aspect ratio constraints, minimum metal wire width, metal-to-metal spacing, metal-fill density, isolation trench/well spacing, diffusion area order and spacing, poly-silicon constraints, ESD-related antenna rules, e.g.

Leading CAD companies support interoperable iPDK however some of mask layout CAD tools work with proprietary design rules.  To enable these CAD layout editors we need to translate the iPDK design rule to the specific, proprietary design rules.

The diploma/master thesis includes tasks:

* Translation of existing iPDK rules into a proprietary format of the specific layout editor by programming scripts.
* Verification of the developed rules in the specific layout editor based on simplest layout structures of transistors, capacitors, resistors.

Required skills:

* Linux/Unix experience and script programming based on Perl, Python, Shell, Tcl/Tk, Skill, C++.
*  Basic understanding of semiconductor VLSI technologies

3. Circuit design of circuit sub-blocks for analog-to-digital converters (ADC) and digital-to-analog converters (DAC)

As part of a Sigma-Delta ADC or current-steering DAC development, various types of analog and digital circuits will be required. Based on a given ADC system specification, individual analog circuit blocks (comparators, operational amplifiers, OTA, sample and hold amplifiers, bandgap references, current biasing) and digital processing circuits (randomizers DEM, DWA, parallel-serial interfaces like JESD204B, SPI programming registers) are to be designed and transferred to the mask layout during the internship or diploma thesis, followed by a layout verification (DRC, LVS) and post-layout simulation. In addition, the designed circuit blocks should be described as high-level models in VerilogA/AMS hardware description languages in order to be able to model non-linearities, mismatch, offset and other errors in a system-level ADC simulation (e.g. calibration algorithms verification).

The diploma/master thesis includes tasks:

* Circuit design, Schematic Entry and SPICE simulation of analog CMOS building blocks
* HDL coding for digital block, synthesis and digital simulation methods (RTL, netlist, STA)
* Physical Mask design (layout) of the developed circuits and their verification (DRC, ERC, LVS)
* Creation of the behavioural models in VerilogA/AMS for this circuit block

Required skills:

* Experience with Cadence or Tanner/Mentor design environment
* Knowledge of appropriate circuit topologies of voltage references, biasing circuits, amplifier architecture
* Unix/Linux skills required

4. Design of a digital decimation filter for a Sigma-Delta modulator ADC

The high-frequency oversampling PCM output signal of a Sigma-Delta modulator (1bit…5bit) is post-processed in the digital domain to digital words with a higher bit width (e.g. 14-16-18 bits) but a lower data rate. To do this, the oversampled modulator signal is first averaged (64-fold down sampler), then the resolution is increased in a digital low-pass filter by filtering out the noise above the usable signal bandwidth. For an existing Sigma-Delta modulator with ~ 90 dB signal-to-noise and distortion ratio (SNDR), a third-order sinc filter (3-stage; with 6, 12, 18 Bit data rate) and a half-band 64th order filter has to be designed so that a resolution of 14-16 bits can be achieved for the entire Sigma-Delta A/D converter . Different digital filter topologies have to be investigated and evaluated for lowest power consumption. The filter is then to be described and simulated in VHDL/Verilog, and synthesized towards transistor netlist for an FPGA and ASIC implementation.

The diploma/master thesis includes tasks:

* Working up the theory and studying the literature on digital decimation filters for the purpose of a appropriate filter topology to be implemented
* Design of the decimation filter (sinc and low-pass filter) as IIR, FIR or wave-digital filters
* HDL coding for digital filter block, synthesis and digital simulation (RTL, netlist, STA)
* Place-and-Route (P&R) layout generation and evaluation of the open source Tool openROAD

Required skills:

* Understanding of digital filter design (FIR, IIR, Wave-digital)
* Experience with Cadence or Synopsys design environment, alternatively openROAD
* Digital signal processing, HDL coding using Verilog or VHDL
* Unix/Linux skills required

5. Literature study and comparison of different calibration and correction algorithms for parallel time-interleaved A/D converters (ADC) towards digital HDL implementation

Based on a literature study, different analog and digital calibration (foreground, background) and correction algorithms for parallel time-interleaved A/D converters have to be compared and suitable architecture selected. The focus in digital domain lies on calibration of inter-channel ADC gain, offset and clock skew calibration, and in the analog domain in the calibration of amplifier’s offset and finite gain. HDL realizations of the selected algorithm for a given ADC architectures has to be implemented.

The diploma/master thesis includes tasks:

* Working up theories and studying the literature on calibration and correction algorithms for ADC
* Behavioral models and simulations (VHDL, Verilog, VerilogA) of the algorithms
* HDL coding, synthesis and digital simulation (RTL, netlist, STA) of the algorithms
* eventually Place-and-Route (P&R) layout generation and evaluation of the open source Tool openROAD

Required skills:

* Understanding of ADC working principles, their non-idealities and errors in circuits
* Experience with Cadence or Synopsys design environment, alternatively openROAD
* Digital signal processing, HDL coding using Verilog or VHDL
* Unix/Linux skills required

6. Evaluation of the automation procedures using Cadence design environment to support script-based systematic simulation and verification strategies for ADC/DAC

What possibilities for simulation automation and monitoring are offered in the following programming and script languages within Cadence design flow

• SKILL

• OCEAN

• VerilogA/AMS behavioural modelling

The diploma/master thesis includes tasks:

* Development of a systematic overview of the structure and the possibilities of the programming and script languages ​​mentioned above
* Writing down a brief  introduction to the programming and script languages
* Programming of a scripts for a parametric and corner simulations using Spice/Spectre
* Automatic compression and postprocessing of the simulation results towards FFT spectral analysis and for usage documentation (figure generation)

Required skills:

* Understanding of ADC/DAC parameters and their simulation approaches (SNR, SNDR, THD, INL, DNL, sampling jitter)
* Experience with Cadence or Mentor design environment
* Unix/Linux skills required